As is known to those skilled in the art, a sense amplifier is one of components that determines an operating speed of a semiconductor memory device. For this reason, a sense amplifier that enables a high operating speed while maintaining its performance may be useful. A latch-type sense amplifier has been proposed as a sense amplifier meeting such requirements.
Various examples of a sense amplifier are disclosed, for example, in Korean Patent Publication No. 2002-9772 entitled “LOW-POWER SENSE AMPLIFIER FOR MEMORY”, Korean Patent Publication No. 2000-41576 entitled “DATA SENSE AMP”, Korean Patent Publication No. 1999-85068 entitled “DRIVING CIRCUIT FOR NONVOLATILE FERROELECTRIC MEMORY DEVICE”, U.S. Pat. No. 5,455,786 entitled “FERROELECTRIC MEMORY”, U.S. Pat. No. 5,959,922 entitled “FERROELECTRIC RANDOM ACCESS MEMORY DEVICE WITH REFERENCE CELL ARRAY BLOCKS”, U.S. Pat. No. 6,169,424 entitled “SELF-BIASING SENSE AMPLIFIER”, Japanese Patent Publication No. 11-219591 entitled “SENSE AMPLIFIER FOR MEMORY ARRAYS”, Japanese Patent Publication No. 12-76856 entitled “SEMICONDUCTOR STORAGE”, and Japanese Patent Publication No. 11-260064 entitled “SENSE AMPLIFIER”.
FIG. 1 is a circuit diagram illustrating a sense amplifier of a conventional semiconductor memory device. As illustrated in FIG. 1, a semiconductor memory device 10 includes a latch-type sense amplifier 12 connected between bit lines BLM and BLR. The sense amplifier 12 includes a pair of PMOS transistors MP0 and MP1 and a pair of NMOS transistors MN0 and MN1. The PMOS transistor MP0 has a current path formed between a signal line SAP and the bit line BLM, and a gate directly coupled to the bit line BLR. The PMOS transistor MP1 has a current path formed between the signal line SAP and the bit line BLR, and a gate directly coupled to the bit line BLM. The NMOS transistor MNO has a current path formed between the bit line BLM and a signal line SAN, and a gate directly coupled to the bit line BLR. The NMOS transistor MN1 has a current path formed between the bit line BLR and the signal line SAN, and a gate directly coupled to the bit line BLM. A memory cell MC is coupled to the bit line BLM, and a reference voltage supply circuit 14 is coupled to the bit line BLR. The reference voltage supply circuit 14 includes a pair of NMOS transistors MN2 and MN3 and a capacitor Cr, which are connected with each other as illustrated in FIG. 1.
FIG. 2 is a timing diagram that illustrates operations of the sense amplifier of FIG. 1. With reference to FIGS. 1 and 2, an operation of the conventional sense amplifier will be now described in detail hereinafter.
As illustrated in FIG. 2, as a control signal REF_EN transitions from a low level to a high level, an electric charge (or charges) corresponding to a VRER voltage are stored in the capacitor Cr via the NMOS transistor MN3. An electric charge amount charged in the capacitor Cr is Cr*VREF. After the electric charges are charged in the capacitor Cr, the control signal REF_EN makes a high-to-low transition. Next, as a control signal DMP_EN transitions from a low level to a high level, the electric charges charged in the capacitor Cr are transferred to the bit line BLR via the NMOS transistor MN2. At the same time, electric charges stored in the memory cell MC are transferred to the bit line BLM. At this time, a voltage of the bit line BLM is higher or lower than that of the bit line BLR. For example, if data ‘1’ is stored in the memory cell MC, a voltage (e.g., 1.1 V) of the bit line BLM is higher than that (e.g., 0.85 V) of the bit line BLR. If data ‘0’ is stored in the memory cell MC, a voltage (e.g., 0.6) of the bit line BLM is lower than that (e.g., 0.85 V) of the bit line BLR. In other words, there is a relatively small voltage difference between the bit lines BLM and BLR. Thereafter, a power supply voltage Vcc is provided to the control signal line SAP, and a ground voltage GND, lower than a predetermined voltage, is provided to the control signal line SAN. That is, the minute voltage difference between the bit lines BLM and BLR is amplified by the sense amplifier.
The foregoing sense amplifier has shortcomings of a reduced sensing margin and a slow sensing speed. If, prior to an operation of the sense amplifier, a voltage difference between the bit lines BLM and BLR is greater than a turn-on voltage or a threshold voltage of the PMOS transistor, a voltage of the bit line BLM is discharged into the signal line SAP of a ground voltage GND which can in turn reduce the sensing margin of the sense amplifier. For example, in the event that the memory cell of data ‘1’ is accessed, a voltage level (e.g., 1.1 V) provided by the memory cell MC can be reduced, and thereby become a low voltage, because of the electrical coupling between the signal line SAP and the bit line BLM. This can lead to a reduction in a voltage difference between the bit lines. Therefore, a sensing margin of the sense amplifier is reduced and a sensing speed is also lowered. Conversely, if, prior to an operation of the sense amplifier, a voltage difference between the bit lines BLM and BLR is greater than a turn-on voltage or a threshold voltage of the NMOS transistor, a predetermined voltage Va of the signal line SAN is provided to the bit line BLM or BLR via the NMOS transistor MN0 thereby possibly changing the respective voltage provided on either the bit line BLM or the bit line BLR. For example, in the event that the memory cell MC provides a data ‘0’, a voltage (e.g., 0.6 V) which would otherwise be provided on the bit line BLM can be increased by the coupling of the voltage from the signal line SAN onto the bit line BLM. This can lead to a reduction in a voltage difference between the bit lines BLM and BLR. Therefore, a sensing margin of the sense amplifier is reduced and a sensing speed is also lowered.
In the case of the conventional reference voltage supply circuit 14, the capacitor Cr is charged with electric charges transferred via the NMOS transistor MN3, and the charged electric charges are transferred to the bit line BLR via the NMOS transistor MN2. For this reason, the sense amplifier may not be operated until after the electric charges in the capacitor Cr are transferred to the bit line BLR. This can reduce the sensing speed of the sense amplifier. Furthermore, because a loading capacitance of the bit line BLM is different from that of the bit line BLR, the sensing performance of the sense amplifier may be affected.
The foregoing reference voltage provided to the sense amplifier circuit can be generated using a paraelectric capacitor that is different from a ferroelectric capacitor of the memory cell. The reference voltage may be generated using a ferroelectric capacitor that is the same as that of the memory cell. Reference voltage generating circuits are disclosed, for example, in U.S. Pat. No. 6,097,624 entitled “METHODS OF OPERATING FERROELECTRIC MEMORY DEVICES HAVING RECONFIGURABLE BIT LINES”. The reference voltage generating circuit of the '624 patent is illustrated in FIG. 3. Referring to FIG. 3, the reference voltage generating circuit 350 includes a pair of NMOS transistors 351 and 353 and a pair of ferroelectric capacitors 352 and 354. The ferroelectric capacitors 352 and 354 of the reference voltage generating circuit 350 are formed to be the same as a ferroelectric capacitor 312 of a memory cell 310. By using the ferroelectric capacitor, a reference voltage may be generated to be similar to a state of the memory cell.
In this case, however, a ferroelectric capacitor of a single reference voltage generating circuit should undertake write/read operations of a plurality of memory cells. This may deteriorate a fatigue characteristic, which is peculiar to ferroelectric materials. With respect to the reference voltage generating circuit 350 of the '624 patent, a reference voltage is generated by applying electric charges of a ferroelectric capacitor to a bit line. That is, the ferroelectric capacitor of the reference voltage generating circuit 350 can have the same distribution of electric charges as that of the memory cell. The distribution of electric charges can make the reference voltage non-uniform (or, the distribution of electric charges can cause the reference voltage to be distributed within a predetermined range). As a result, the sensing margin of the sensing amplifier can be reduced.